[1]李艳龙,杨 琪,王雪峰.基于SV-DPI的图像坏元修正FPGA自动化验证[J].红外技术,2020,42(12):1192-1197.[doi:doi:10.11846/j.issn.1001_8891.202012010]
　LI Yanlong,YANG Qi,WANG Xuefeng.Automatic Verification of Field Programmable Gate Arrays for Dead Pixel Correction [J].Infrared Technology,2020,42(12):1192-1197.[doi:doi:10.11846/j.issn.1001_8891.202012010]
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基于SV-DPI的图像坏元修正FPGA自动化验证
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《红外技术》[ISSN:1001-8891/CN:CN 53-1053/TN]

卷:
42卷
期数:
2020年第12期
页码:
1192-1197
栏目:
出版日期:
2020-12-22

文章信息/Info

Title:
Automatic Verification of Field Programmable Gate Arrays
for Dead Pixel Correction
文章编号:
1001-8891(2020)12-1192-06
作者:
李艳龙; 杨 琪; 王雪峰
西安微电子技术研究所，陕西 西安 710065
Author(s):
LI Yanlong; YANG Qi; WANG Xuefeng
 Xi’an Microelectronic Technique Institute, Xi’an 710065, China
关键词:
自动化测试; FPGA验证; 红外图像坏元修正; 验证平台
Keywords:
automated testing;  FPGA verification;  dead pixel correction of infrared image;  verification platform
分类号:
TP306
DOI:
doi:10.11846/j.issn.1001_8891.202012010
文献标志码:
A
摘要:
为实现红外图像坏元修正FPGA（field programmable gate array）的快速验证，提高测试覆盖性，设计了基于SV-DPI（SystemVerilog-direct programming interface）的FPGA自动化验证平台。采用DPI（direct programming interface）编程接口技术，实现了SystemVerilog平台调用C＋＋编程语言，构建了针对红外图像坏元数据的生成和检测修正模型，建立了两种语言在事务级（transaction level）模型的通信。结果表明相对于传统验证方法，该平台结构简单，可以快速实现激励产生、参考模型构建、测试结果自动比对等功能，实现了红外图像坏元检测与修正FPGA的自动化测试，功能覆盖率达到100%，有效缩短FPGA测试平台搭建和调试周期，提高了测试效率和测试质量。
Abstract:
To accelerate the simulation speed and improve the coverage of verification for a field programmable gate array (FPGA) implemented with dead pixel correction of an infrared image, an FPGA automatic verification platform based on SystemVerilog-Direct programming interface(SV-DPI) was designed. Using DPI programming interface technology, the C++ programming language was invoked by the SV platform. A generator and correction model for dead pixel data of infrared images was built. This established a communication between two languages on the transaction level. The results show that, compared with the traditional verification method, the proposed platform is simple in structure and can quickly generate a test vector, construct a reference model, and check results automatically. It realizes automated verification for an FPGA implemented with dead pixel detection and correction of an infrared image. The function coverage can reach 100%. It effectively shortens the period of construction and debugging for the FPGA verification platform and improves the efficiency and quality of verification.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期：2020-04-20；修订日期：2020-06-21.
作者简介：李艳龙（1988-），男，吉林白城人，工程师，硕士。研究方向为FPGA测试、测试自动化技术。E-mail：470968999@qq.com。
更新日期/Last Update: 2020-12-21